Entering upon the 21st century, the whole world has entered the information society. The information society is a community where people can come into contact with and freely use information anywhere any time. Rapid progress of microprocessors, above all else, can be regarded as the biggest technical factor enabling such information society. Since Intel announced the first microprocessor in the world, the 4004 microprocessor composed of 2,250 transistors with a 10-micron line width and having a speed of 108 KHz, in 1971, Samsung Electronics Co., Ltd. announced the Alpha processor running at 1 GHz in 2000 and Intel announced the 3 GHz Pentium 4 in December, 2002, so that microprocessor technology has now entered the age of “Beyond GHz”. It is expected that an 11 GHz microprocessor in which one hundred million transistors with a 40-nanometer line width are integrated will be developed by 2010.
However, various problems occur as microprocessors become higher in integration and performance. Firstly, a System-on-Chip (SoC) increases in volume, resulting in increases in clock skew and clock frequency. As a result, the period of one cycle is shortened, thereby increasing the burden of jitter. Secondly, the higher the integration, the higher the power density, so there is also a need to take a low-power design into consideration.
Hence, research has been conducted into the design of a low-jitter, high-speed locking first-order phase locked loop (PLL) of a non-voltage-controlled oscillator (non-VCO) type useful to the design of a high-speed SoC. Most of the existing clock generators have employed PLLs with VCOs. However, the VCO is disadvantageous in that it not only accumulates jitter in output thereof for several oscillation periods, but also makes slow changes to various operation modes which are essential to low-power applications. In contrast, because a voltage-controlled delay line (VCDL) of a delay locked loop (DLL) is an open loop, it has the advantage of accumulating no jitter and being rapidly re-locked when switching operation modes. In addition, the DLL maintains stability with a first-order system and has a loop filter easy to integrate. However, since the DLL does not employ a frequency divider, it has difficulty in frequency multiplication and, in turn, high-speed clock generation. The following Table 1 shows a comparison in advantages and disadvantages between the PLL and the DLL.
TABLE 1PLLDLLVCOVCDLjitter accumulated (closed loop)no jitter accumulated (open loop)higher-order systemfirst-order systemsometimes unstablealways stabledifficult to designeasy to designlarge area required to integrate loopeasy to integrate loop filterfilterlittle influenced by reference signalinfluenced by reference signaljitter characteristicsjitter characteristicseasy to multiply frequencydifficult to multiply frequency
Therefore, a low-jitter, high-speed locking first-order PLL will be designed to lock a high-speed clock signal on the basis of a DLL with such various advantages. To this end, first, a high-speed frequency multiplier will be designed with improved error. As a result, it will be possible to generate a low-jitter, high-speed clock signal even with the DLL. Next, frequency multiplication will be dynamically performed so that a microprocessor can operate at a frequency optimal to a given state. Finally, the clock of a frequency obtained as a result of the frequency multiplication will be synchronized with an input clock, thereby making it possible to replace a PLL which is an existing high-speed clock generator with a low-jitter, high-speed locking first-order PLL which operates more stably.
FIGS. 1 and 2 are block diagrams of two typical high-speed clock generators. FIG. 1 shows the configuration of a high-speed clock generator based on a PLL. The PLL-based clock generator includes a VCO and two frequency dividers. One of the frequency dividers is a 1/N-frequency divider which multiplies the frequency of a reference input signal by N, and the other is a ½-frequency divider which allows the output of the VCO to have a duty ratio of 50%. This PLL-based clock generator has a disadvantage in that jitter is accumulated in the output of the VCO. That is, as shown in FIG. 3a, if power noise is present in the VCO, the edge of each clock of the VCO is subject to phase distortion, which is continuously accumulated. In contrast, a DLL using a VCDL has the advantage of basically prohibiting the accumulation of jitter. Namely, as shown in FIG. 3b, because the VCDL is an open loop, jitter has no effect on the next clock period even though it occurs.
Accordingly, a frequency multiplier is an important block in designing a high-speed clock generator based on the DLL. In the last 2 to 3 years, some frequency multiplication techniques using the DLL have been reported and have shown that a low-jitter clock generator and low-phase error local oscillator using the DLL are excellent. For example, one frequency multiplication technique using the DLL may be a DLL-based local oscillator for personal communication service (PCS) which performs a frequency multiplication operation using an edge combiner. Another technique may be a DLL-based frequency synthesizer using AND and OR gates which obtains a frequency multiplication ratio of 9 so that it can generate a high-speed clock signal of 1 GHz. However, in the frequency multiplier for the PCS, an LC tank of an output node which is used to increase a load impedance at a resonance frequency requires a large area, and an inductor with a low Q value which is used to obtain low close-in phase noise must allow a large amount of current to flow therethrough, in order to obtain desired output swing.
The frequency multiplier for the PCS has a further disadvantage in that the multiplication ratio cannot be changed once the value of the LC tank is decided. The DLL-based frequency synthesizer using the AND and OR gates has a limitation in reducing peak-to-peak jitter because the AND and OR gates are sensitive to power noise. Further, the frequency synthesizer is disadvantageous in that a pull-up resistor of 50Ω must be provided outside of a chip so as to be used for an analog input/output buffer and the multiplication ratio is fixed.